From: Dave Hansen <dave.hansen@linux.intel.com>
To: dave.hansen@linux.intel.com
Subject: Re: [PATCH v9 09/23] coco/tdx-host: Don't expose P-SEAMLDR information on CPUs with erratum
In-Reply-To: <20260513151045.1420990-10-chao.gao@intel.com>
References: <20260513151045.1420990-10-chao.gao@intel.com>
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[Draft review generated by x86-maintainer-agent applying Dave_Hansen.txt
 rules to the v9 series.  Strip this banner before sending.]

> +static void __init check_tdx_erratum(void)
> +{
> +	u64 basic_msr;
> ...
> +	rdmsrq(MSR_IA32_VMX_BASIC, basic_msr);
> +	if (!(basic_msr & VMX_BASIC_NO_SEAMRET_INVD_VMCS))
> +		setup_force_cpu_bug(X86_BUG_SEAMRET_INVD_VMCS);
> +}

Add a one-liner reminding the reader that MSR_IA32_VMX_BASIC is
unconditionally available on every TDX-capable CPU (because TDX
requires VMX).  Otherwise the next maintainer to touch
check_tdx_erratum() will quite reasonably wonder whether this rdmsrq
needs a feature-bit guard.  Dave_Hansen.txt RULE 17.

The use of X86_BUG_* + a name on /proc/cpuinfo lines up exactly with
RULE 4, the alternatives section walks through the two rejected
workarounds (RULE 1), and the cross-reference to the V8 thread is in
the Link: tag (RULE 16).  This patch is a model for how the rest of
the series should look.

Reviewed-by: Dave Hansen <dave.hansen@linux.intel.com>  [with the
                                                        rdmsrq note]